1. Field of the Invention
This invention relates to data processing apparatus and a method of operating a data processing apparatus. More particularly, this invention relates to a data processing apparatus that is operable in either a main processing mode or one or more exception processing modes.
2. Description of the Prior Art
It is known to provide central processing units (CPUs) that are operable in both a main processing mode and one or more exception processing modes. The main processing mode is used for execution of the application software for performing the user's desired data processing. The exception processing modes are usually used for operations such as responding to externally applied interrupt signals.
It is desirable that the move between the main processing mode and the exception processing mode should be reversible in that when a return is made to the main processing mode the operation of the main processing mode will continue as if it had not been interrupted. In order to achieve such reversibility, it is necessary that the contents of the various processing registers within the CPU should be saved upon leaving the main processing mode so that they can be restored after the exception processing mode has finished its use of the registers and control is returned to the main processing mode. This is conventionally achieved by saving the contents of the registers in the main processing mode to an area of stack memory in external random access memory (RAM) upon leaving the main processing mode and then returning these contents from the area of stack memory to the registers upon returning to the main processing mode.
A problem with this conventional approach is that the operations of writing to and subsequently reading from a stack memory is relatively slow and thus degrades the performance of the CPU.
Another problem in such conventional approaches is that processing overhead must also be expended to save and restore processing status data (e.g. various status flags specifying the desired/permitted operation of the CPU) when leaving and re-entering the main processing mode.